This document is a specification for the register interface of the FPGA module simple_dma.
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The following register modes are available.
| Mode | Description |
|---|---|
| Read | Software can read a value that hardware provides. |
| Write | Software can write a value that is available for hardware usage. |
| Read, Write | Software can write a value and read it back. The written value is available for hardware usage. |
| Write-pulse | Software can write a value that is asserted for one clock cycle in hardware. |
| Read, Write-pulse | Software can read a value that hardware provides. Software can write a value that is asserted for one clock cycle in hardware. |
The following registers make up the register map.
| Name | Index | Address | Mode | Default value | Description |
|---|---|---|---|---|---|
| interrupt_status | 0 | 0x0000 | Read, Write-pulse | 0x0 | Interrupt status for the different interrupt sources of this module. When an interrupt condition occurs, the corresponding bit in this register will read as '1' until cleared (see below). If the corresponding bit in interrupt_mask is also set to '1' by software, the interrupt signal of this module will trigger, meaning it will be '1' until the interrupt(s) that triggered it are cleared. Note that if an interrupt-based workflow is not used, this register can instead be polled to check for events. Interrupt status is cleared by writing '1' to the target interrupt bit(s) in this register. |
| write_done | 0 | 0b0 | A streaming packet, as defined by the packet_length_beats generic, has been written to memory. Compare buffer_written_address with buffer_read_address to find out how many bytes have been written and to which location. | ||
| write_error | 1 | 0b0 | Memory write responded with error (BRESP). | ||
| start_address_unaligned_error | 2 | 0b0 | The provided buffer_start_address is not aligned with the burst length. | ||
| end_address_unaligned_error | 3 | 0b0 | The provided buffer_end_address is not aligned with the burst length. | ||
| read_address_unaligned_error | 4 | 0b0 | The provided buffer_read_address is not aligned with the burst length. | ||
| interrupt_mask | 1 | 0x0004 | Read, Write | 0x0 | Interrupt enable mask for the different interrupts of this module. The bits of this register correspond to the interrupts in interrupt_status. Clearing the mask of an interrupt will lower the interrupt signal of this module, if the interrupt trigger was caused by that specific interrupt. |
| config | 2 | 0x0008 | Read, Write | 0x0 | Configuration register. |
| enable | 0 | 0b0 |
When this bit is set, the module will continuously consume streaming data and write it to the memory buffer. Before this bit is set, the module will stall streaming data (stream_ready tied low). Before this bit is set, the buffer_start_address, buffer_end_address, and buffer_read_address registers must be set with valid values. The module does not support disabling after enabling. I.e, once this bit has been set, clearing it will result in an undefined behavior. |
||
| buffer_start_address | 3 | 0x000C | Write | 0x0 | Address to the first byte in the memory buffer. Must be aligned by the burst length expressed in bytes. This address and upcoming bytes after will be written with data. Note that while a 32-bit value can be written to this register, only the number of bits given by the address_width generic will actually be used by the module. Once this value has been set, and the module enable'd, the value must not be changed. |
| buffer_end_address | 4 | 0x0010 | Write | 0x0 | Address to the byte after the last byte in the memory buffer. Must be aligned by the burst length expressed in bytes. Bytes before this address (excluding) will be written with data. Note that while a 32-bit value can be written to this register, only the number of bits given by the address_width generic will actually be used by the module. Once this value has been set, and the module enable'd, the value must not be changed. |
| buffer_written_address | 5 | 0x0014 | Read | 0x0 | Is continuously updated by the module as data is written to the memory buffer. All bytes between buffer_read_address (including) and this address (excluding) will contain valid written data. That number of bytes will always be a multiple of the burst length expressed in bytes. If buffer_read_address and this address are equal, the memory buffer is empty. If they have different values, the memory buffer contains valid written data. When the module reaches the end of the buffer, i.e. when the very last byte of the buffer has been written, the value of this register will wrap around to buffer_start_address. I.e. this register will never assume the value of buffer_end_address. The value of this register will always be aligned by the burst length expressed in bytes. Note that while a 32-bit value is read from this register, only the number of bits given by the address_width generic will actually be set by the module. The others will always read as zero. |
| buffer_read_address | 6 | 0x0018 | Write | 0x0 | Must be continuously updated by the software as it consumes data from the memory buffer. All bytes before (excluding) this address are considered free and can be written by the module. When data is written to the memory buffer, the software must consume all the data between this address (including) and buffer_written_address (excluding). Once this is done, the software must update this register with the value of buffer_written_address. When that is done, this part of the memory buffer can be written again by the module. Meaning, at that point, software must either be fully finished with the data or have a copy of it. The value written to this register must be aligned by the burst length expressed in bytes. Note that while a 32-bit value can be written to this register, only the number of bits given by the address_width generic will actually be used by the module. |
This module does not have any constants.