.. _module_axi_lite: Module axi_lite =============== This document contains technical documentation for the ``axi_lite`` module. To browse the source code, please visit the `repository on GitHub `__. This module contains a large set of AXI-Lite components written in VHDL. They are based around record types in :ref:`axi_lite.axi_lite_pkg` that make it convenient to work with the AXI-Lite signals. See also the :ref:`module_bfm` for tools to efficiently simulate your AXI-Lite design. .. _axi_lite.axi_lite_cdc: axi_lite_cdc.vhd ---------------- `View source code on GitHub `__. .. symbolator:: component axi_lite_cdc is generic ( data_width : positive range 1 to axi_lite_data_sz; addr_width : positive range 1 to axi_a_addr_sz; fifo_depth : positive; ram_type : ram_style_t ); port ( clk_master : in std_ulogic; master_m2s : in axi_lite_m2s_t; master_s2m : out axi_lite_s2m_t; --# {{}} clk_slave : in std_ulogic; slave_m2s : out axi_lite_m2s_t; slave_s2m : in axi_lite_s2m_t ); end component; Clock domain crossing of a full AXI-Lite bus (read and write) using asynchronous FIFOs for the different channels. By setting the width generics, the bus is packed optimally so that no unnecessary resources are consumed. .. note:: The constraints of :ref:`fifo.asynchronous_fifo` must be used. .. _axi_lite.axi_lite_mux: axi_lite_mux.vhd ---------------- `View source code on GitHub `__. .. symbolator:: component axi_lite_mux is generic ( base_addresses : addr_vec_t ); port ( clk : in std_ulogic; --# {{}} axi_lite_m2s : in axi_lite_m2s_t; axi_lite_s2m : out axi_lite_s2m_t; --# {{}} axi_lite_m2s_vec : out axi_lite_m2s_vec_t; axi_lite_s2m_vec : in axi_lite_s2m_vec_t ); end component; AXI-Lite mux, aka simple 1-to-N crossbar. The ``base_addresses`` generic is a list of base addresses for the N slaves. If the address requested by the master does not match any base address, this entity will send AXI decode error ``DECERR`` on the response channel (``RRESP`` or ``BRESP``). There will still be proper AXI handshaking done, so the master will not be stalled. .. warning:: This entity is written to be used in a register bus, and is designed for simplicity and low resource utilization. An assumption is made that the AXI-Lite master does not queue up reads or writes. I.e. after an ``AR`` transaction, it does not send another ``ARVALID`` before the ``R`` transaction has happened. Same for ``AW`` and ``W``/``B``. If the AXI-Lite does queue up transactions it can lead to locking the bus. However, if you are using this entity then you probably have a :ref:`axi_lite.axi_to_axi_lite` instance upstream. This entity will by design not queue up transactions. .. _axi_lite.axi_lite_mux.resource_utilization: Resource utilization ____________________ This entity has `netlist builds `__ set up with `automatic size checkers `__ in `module_axi_lite.py `__. The following table lists the resource utilization for the entity, depending on generic configuration. .. list-table:: Resource utilization for **axi_lite_mux** netlist builds. :header-rows: 1 * - Generics - Total LUTs - FFs - Maximum logic level * - (Using wrapper axi_lite_mux_netlist_build_wrapper.vhd) - 516 - 28 - 5 .. _axi_lite.axi_lite_pipeline: axi_lite_pipeline.vhd --------------------- `View source code on GitHub `__. .. symbolator:: component axi_lite_pipeline is generic ( data_width : positive range 1 to axi_lite_data_sz; addr_width : positive range 1 to axi_a_addr_sz; full_throughput : boolean; pipeline_control_signals : boolean ); port ( clk : in std_ulogic; --# {{}} master_m2s : in axi_lite_m2s_t; master_s2m : out axi_lite_s2m_t; --# {{}} slave_m2s : out axi_lite_m2s_t; slave_s2m : in axi_lite_s2m_t ); end component; Pipelining of a full AXI-Lite bus (read and write), with the goal of improving timing on the data and/or control signals. The default settings will result in full skid-aside buffers, which pipeline both the data and control signals. However the generics to :ref:`common.handshake_pipeline` can be modified to get a simpler implementation that results in lower resource utilization. .. _axi_lite.axi_lite_pkg: axi_lite_pkg.vhd ---------------- `View source code on GitHub `__. Data types for working with AXI4-Lite interfaces. Based on the document "ARM IHI 0022E (ID022613): AMBA AXI and ACE Protocol Specification" Available here: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0022e/ .. _axi_lite.axi_lite_simple_read_crossbar: axi_lite_simple_read_crossbar.vhd --------------------------------- `View source code on GitHub `__. .. symbolator:: component axi_lite_simple_read_crossbar is generic ( num_inputs : positive ); port ( clk : in std_ulogic; --# {{}} input_ports_m2s : in axi_lite_read_m2s_vec_t; input_ports_s2m : out axi_lite_read_s2m_vec_t; --# {{}} output_m2s : out axi_lite_read_m2s_t; output_s2m : in axi_lite_read_s2m_t ); end component; Simple N-to-1 crossbar for connecting multiple AXI-Lite read masters to one port. This is a wrapper around :ref:`axi.axi_simple_read_crossbar`. See that entity for details. .. _axi_lite.axi_lite_simple_write_crossbar: axi_lite_simple_write_crossbar.vhd ---------------------------------- `View source code on GitHub `__. .. symbolator:: component axi_lite_simple_write_crossbar is generic ( num_inputs : positive ); port ( clk : in std_ulogic; --# {{}} input_ports_m2s : in axi_lite_write_m2s_vec_t; input_ports_s2m : out axi_lite_write_s2m_vec_t; --# {{}} output_m2s : out axi_lite_write_m2s_t; output_s2m : in axi_lite_write_s2m_t ); end component; Simple N-to-1 crossbar for connecting multiple AXI-Lite write masters to one port. This is a wrapper around :ref:`axi.axi_simple_write_crossbar`. See that entity for details. .. _axi_lite.axi_lite_to_vec: axi_lite_to_vec.vhd ------------------- `View source code on GitHub `__. .. symbolator:: component axi_lite_to_vec is generic ( base_addresses : addr_vec_t; clocks_are_the_same : boolean_vector; cdc_fifo_depth : positive; cdc_ram_type : ram_style_t; pipeline_slaves : boolean ); port ( --# {{}} clk_axi_lite : in std_ulogic; axi_lite_m2s : in axi_lite_m2s_t; axi_lite_s2m : out axi_lite_s2m_t; --# {{}} clk_axi_lite_vec : in std_ulogic_vector; axi_lite_m2s_vec : out axi_lite_m2s_vec_t; axi_lite_s2m_vec : in axi_lite_s2m_vec_t ); end component; Convenience wrapper for splitting and CDC'ing a register bus based on generics. The goal is to split a register bus, and have each resulting AXI-Lite bus in the same clock domain as the module that uses the registers. Typically used in chip top levels. Instantiates :ref:`axi_lite.axi_lite_mux` and :ref:`axi_lite.axi_lite_cdc`. .. _axi_lite.axi_to_axi_lite: axi_to_axi_lite.vhd ------------------- `View source code on GitHub `__. .. symbolator:: component axi_to_axi_lite is generic ( data_width : positive range 1 to axi_lite_data_sz ); port ( clk : in std_ulogic; --# {{}} axi_m2s : in axi_m2s_t; axi_s2m : out axi_s2m_t; --# {{}} axi_lite_m2s : out axi_lite_m2s_t; axi_lite_s2m : in axi_lite_s2m_t ); end component; Convert AXI transfers to AXI-Lite transfers. This module does not handle conversion of non-well behaved AXI transfers. Burst length has to be one and size must be the width of the bus. If these conditions are not met, the read/write response will signal ``SLVERR``. This module will throttle the AXI bus so that there is never more that one outstanding transaction (read and write separate). While the AXI-Lite standard does allow for outstanding bursts, some Xilinx cores (namely the PCIe DMA bridge) do not play well with it. .. _axi_lite.axi_to_axi_lite_vec: axi_to_axi_lite_vec.vhd ----------------------- `View source code on GitHub `__. .. symbolator:: component axi_to_axi_lite_vec is generic ( base_addresses : addr_vec_t; clocks_are_the_same : boolean_vector; pipeline_axi_lite : boolean; pipeline_slaves : boolean ); port ( clk_axi : in std_ulogic; axi_m2s : in axi_m2s_t; axi_s2m : out axi_s2m_t; --# {{}} clk_axi_lite_vec : in std_ulogic_vector; axi_lite_m2s_vec : out axi_lite_m2s_vec_t; axi_lite_s2m_vec : in axi_lite_s2m_vec_t ); end component; Convenience wrapper for converting a AXI bus to AXI-Lite, and then splitting and CDC'ing a register bus. The goal is to split a register bus, and have each resulting AXI-Lite bus in the same clock domain as the module that uses the registers. Typically used in chip top levels. Instantiates :ref:`axi_lite.axi_to_axi_lite`, :ref:`axi_lite.axi_lite_mux` and :ref:`axi_lite.axi_lite_cdc`.