.. _module_axi_stream: Module axi_stream ================= This document contains technical documentation for the ``axi_stream`` module. To browse the source code, please visit the `repository on GitHub `__. This module contains a set of AXI-Stream components written in VHDL. They are based around record types in :ref:`axi_stream.axi_stream_pkg` that make it convenient to work with the AXI-Stream signals. See also the :ref:`module_bfm` for tools to efficiently simulate your AXI-Stream design. .. _axi_stream.axi_stream_fifo: axi_stream_fifo.vhd ------------------- `View source code on GitHub `__. .. symbolator:: component axi_stream_fifo is generic ( data_width : positive range 1 to axi_stream_data_sz; user_width : natural range 0 to axi_stream_user_sz; asynchronous : boolean; depth : positive; ram_type : ram_style_t ); port ( clk : in std_ulogic; clk_output : in std_ulogic; --# {{}} input_m2s : in axi_stream_m2s_t; input_s2m : out axi_stream_s2m_t; --# {{}} output_m2s : out axi_stream_m2s_t; output_s2m : in axi_stream_s2m_t ); end component; FIFO for AXI Stream. Can be used as clock crossing by setting the ``asynchronous`` generic. By setting the width generics, the bus is packed optimally so that no unnecessary resources are consumed. .. note:: If asynchronous operation is enabled, the constraints of :ref:`fifo.asynchronous_fifo` must be used. .. _axi_stream.axi_stream_pkg: axi_stream_pkg.vhd ------------------ `View source code on GitHub `__. Data types for working with AXI4-Stream interfaces. Based on the document "ARM IHI 0051A (ID030610) AMBA 4 AXI4-Stream Protocol Specification" Available here: https://developer.arm.com/documentation/ihi0051/a/