.. _release_notes: Release notes ============= Release history and changelog for the hdl-modules project. We follow the `semantic versioning `__ scheme ``MAJOR.MINOR.PATCH``: * ``MAJOR`` is bumped when incompatible API changes are made. * ``MINOR`` is bumped when functionality is added in a backward-compatible manner. * ``PATCH`` is bumped when backward-compatible bug fixes are made. Unreleased (YYYY-MM-DD) ----------------------- `Changes since previous release `__ Fixes * Fix ``ARREADY`` handshaking bug in :ref:`register_file.axi_lite_register_file`. * Fix bug in :ref:`axi.axi_simple_read_crossbar`, :ref:`axi.axi_simple_write_crossbar`, :ref:`axi_lite.axi_lite_simple_read_crossbar` and :ref:`axi_lite.axi_lite_simple_write_crossbar`. * Fix limitation/bug in :ref:`axi_lite.axi_lite_mux`. Breaking changes * Use more-compact VUnit mechanism for getting random seed in BFMs. Removes the ``seed`` generic from * :ref:`bfm.handshake_master` * :ref:`bfm.handshake_slave` * :ref:`bfm.axi_stream_master` * :ref:`bfm.axi_stream_slave` * :ref:`bfm.axi_read_master` * :ref:`bfm.axi_write_master` 6.2.1 (1 may 2025) ------------------ `Changes since previous release `__ Fixes * Improvements in AXI write DMA :ref:`dma_axi_write_simple_cpp`. 6.2.0 (31 march 2025) --------------------- `Changes since previous release `__ Added * Add reset support to :ref:`register_file.axi_lite_register_file`. 6.1.0 (25 march 2025) --------------------- `Changes since previous release `__ Added * Add :ref:`math.truncate_round_signed`. * Add :ref:`common.event_aggregator`. * Add ``write_done`` interrupt aggregation mechanism to :ref:`module_dma_axi_write_simple`. 6.0.0 (18 january 2025) ----------------------- `Changes since previous release `__ Added * Add :ref:`module_dma_axi_write_simple`. * Add :ref:`common.assign_last`. * Add :ref:`resync.resync_rarely_valid` and :ref:`resync.resync_rarely_valid_lutram`. * Add :ref:`resync.resync_sticky_level`. * Add :ref:`resync.resync_twophase_lutram`. Fixed * Fix bug where :ref:`fifo.asynchronous_fifo` constraint would fail on UltraScale+ devices when FIFO mapped to LUTRAM primitives. Breaking changes * Rename ``resync_slv_level_coherent`` to :ref:`resync.resync_twophase`. * Rename ``resync_slv_handshake`` to :ref:`resync.resync_twophase_handshake`. * Rename :ref:`common.common_pkg` function ``ite`` to ``if_then_else``. * Rename old ``reg_file`` module to :ref:`register_file ` and rework it. Note that this change is compatible with `hdl-registers `__ version 7.0.0 and later. If you use hdl-registers, the changes should be transparent. The changes are: * Rename "reg" to "register", "idx" to "index", "reg_type" to "mode" for all files, types, constants. * Add ``utilized_width`` field to register definition type. * Optimize resource utilization of :ref:`register_file.axi_lite_register_file`. * Remove unused functions. 5.0.1 (9 july 2024) ------------------- `Changes since previous release `__ Added * Add ``resync_slv_handshake``. * Add ``enable_iob`` generic to :ref:`common.debounce`. Bug fixes * Respect the ``include_unisim`` flag in ``module_hard_fifo.get_simulation_files`` method. * Ensure deterministic latency of :ref:`resync.resync_pulse`, ``resync_slv_level_coherent``, and :ref:`common.debounce`. Other changes * Waive irrelevant Vivado CDC warnings to make reports more clean. 5.0.0 (8 may 2024) ------------------ `Changes since previous release `__ Added * Add :ref:`module_sine_generator`. * Add :ref:`module_lfsr`. * Add :ref:`math.saturate_signed`. Internal changes * Optimize library and package imports in a way that decreases simulation time by 20-40% for small testbenches using GHDL. Breaking changes * Remove protocol checking from :ref:`bfm.handshake_master` and :ref:`bfm.handshake_slave`. If protocol checking is still wanted in places where these are instantiated, an :ref:`common.axi_stream_protocol_checker` instance alongside is recommended. * Split ``bfm.bfm_pkg`` into * :ref:`bfm.stall_bfm_pkg` * :ref:`bfm.axi_slave_bfm_pkg` * :ref:`bfm.integer_array_bfm_pkg` * :ref:`bfm.queue_bfm_pkg` * :ref:`bfm.memory_bfm_pkg`. * Change ``stall_config`` generic of * :ref:`bfm.handshake_master` * :ref:`bfm.handshake_slave` * :ref:`bfm.axi_stream_master` * :ref:`bfm.axi_stream_slave` * :ref:`bfm.axi_read_master` * :ref:`bfm.axi_write_master` to use type ``stall_configuration_t`` from :ref:`bfm.stall_bfm_pkg`. 4.0.0 (25 january 2024) ----------------------- `Changes since previous release `__ Added * Implement our own lightweight :ref:`common.axi_stream_protocol_checker` that greatly reduces CPU cycles consumed during simulation. * Add :ref:`axi.axi_read_range_checker` and :ref:`axi.axi_write_range_checker`. * Add ``user`` port to :ref:`common.width_conversion`. Fixes * Fix bug in :ref:`register_file.axi_lite_register_file` where a non-zero default value for a register of mode ``wpulse`` or ``r_wpulse`` would only be asserted on ``regs_down`` the very first clock cycle. * Fix bug where :ref:`axi.axi_read_throttle` could lower ``ARVALID`` without an AR transaction having occurred. Breaking changes * Remove unused ``addr_width`` generic from :ref:`bfm.axi_read_master` and :ref:`bfm.axi_write_master`. * Rename :ref:`axi_lite.axi_lite_mux` generic ``slave_addrs`` to ``base_addresses`` and change type to ``addr_vec_t``, i.e. a list of base addresses. Same for :ref:`axi_lite.axi_lite_to_vec` generic ``axi_lite_slaves``. The address mask is now calculated internally. * Rename optional :ref:`bfm.axi_write_master` generic ``set_axi3_w_id`` to ``enable_axi3``. * Remove optional ``rule_4_performance_check_max_waits`` generic from :ref:`bfm.handshake_master` and :ref:`bfm.handshake_slave` which is not needed by new :ref:`common.axi_stream_protocol_checker`. * Break :ref:`axi ` module into :ref:`axi_lite ` and :ref:`axi_stream `. * Move from :ref:`axi ` to :ref:`axi_lite `: * :ref:`axi_lite.axi_lite_cdc`. * :ref:`axi_lite.axi_lite_mux`. * :ref:`axi_lite.axi_lite_pipeline`. * :ref:`axi_lite.axi_lite_pkg`. * :ref:`axi_lite.axi_lite_simple_read_crossbar`. * :ref:`axi_lite.axi_lite_simple_write_crossbar`. * :ref:`axi_lite.axi_lite_to_vec`. * :ref:`axi_lite.axi_to_axi_lite_vec`. * :ref:`axi_lite.axi_to_axi_lite`. * Move from :ref:`axi ` to :ref:`axi_stream `: * :ref:`axi_stream.axi_stream_fifo`. * :ref:`axi_stream.axi_stream_pkg`. 3.0.2 (27 september 2023) ------------------------- `Changes since previous release `__ Added * Add ``num_bits_needed_signed`` to :ref:`math.math_pkg`. 3.0.1 (27 september 2023) ------------------------- `Changes since previous release `__ Added * Add ``stable_rising_edge`` and ``stable_falling_edge`` ports to :ref:`common.debounce`. * Add :ref:`common.handshake_merger`. 3.0.0 (2 march 2023) -------------------- `Changes since previous release `__ Added * Add :ref:`common.handshake_mux`. * Add :ref:`common.clean_packet_dropper`. * Add :ref:`common.time_pkg`. Bug fixes * Fix bug where :ref:`fifo.fifo` in packet mode could propagate erroneous data when a packet of length one was written to an almost empty FIFO. * Fix bug where :ref:`fifo.fifo` and :ref:`fifo.asynchronous_fifo` in packet mode could have bubble cycles in packet readout when output register was enabled. * Fix bug where :ref:`bfm.axi_stream_master`, :ref:`bfm.axi_write_master` and :ref:`bfm.axi_read_master` would not drive bus with ``'X'`` when ``valid`` was low. Breaking changes * Rename :ref:`bfm.axi_stream_slave` port ``num_bursts_checked`` to ``num_packets_checked``. * Rename :ref:`common.width_conversion` generic ``support_unaligned_burst_length`` to ``support_unaligned_packet_length``. * Remove the ``remove_strobed_out_invalid_data`` generic from :ref:`bfm.axi_stream_slave` and :ref:`bfm.axi_write_slave`. This behavior is now always enabled. * Change to use unresolved VHDL types consistently. * ``std_ulogic`` instead of ``std_logic``. * ``std_ulogic_vector`` instead of ``std_logic_vector``. * ``u_signed`` instead of ``signed``. * ``u_unsigned`` instead of ``unsigned``. * Move ``to_period`` and ``to_frequency_hz`` functions from :ref:`common.types_pkg` to :ref:`common.time_pkg`. * Remove erroneous assignment of ``asynchronous_fifo`` port ``read_level`` when packet mode is enabled. * Remove the rarely used ``axi_w_fifo`` port ``read_level`` which does not have valid value in all configurations. * Remove the rarely used ``axi_write_cdc`` port ``output_data_fifo_level`` which does not have valid value in all configurations. 2.0.0 (24 august 2022) ---------------------- `Changes since previous release `__ Added * Add :ref:`common.handshake_pipeline` generic ``pipeline_data_signals`` with default value ``true``, and implement mode that pipelines control signals but not data. * Add :ref:`fifo.fifo` and :ref:`fifo.asynchronous_fifo` generic ``enable_output_register`` with default value ``false``, which adds a pipeline stage for RAM output data. * Add :ref:`bfm.axi_read_master` and :ref:`bfm.axi_write_master` BFMs that create and verify AXI transactions. * Add :ref:`axi.axi_read_pipeline` and :ref:`axi.axi_write_pipeline` blocks that pipeline an AXI bus. Bug fixes * Fix full throughput in :ref:`common.keep_remover` when not all input lanes are strobed. * Fix bug in :ref:`axi.axi_write_throttle` where rogue ``AW`` transactions could occur. * Fix handling of handshake signals in :ref:`common.handshake_splitter` to be AXI-Stream compliant. Breaking changes * Rework :ref:`common.handshake_splitter` to use ``std_logic_vector`` for ``output_ready`` and ``output_valid``. Introduce mandatory generic ``num_interfaces``. * Change :ref:`common.handshake_pipeline` and :ref:`axi_lite.axi_lite_pipeline` generics ``allow_poor_input_ready_timing`` with default value ``false`` to ``pipeline_control_signals`` with default value ``True``. * Rename :ref:`bfm.axi_stream_slave` and :ref:`bfm.handshake_slave` generic ``remove_strobed_out_dont_care`` to ``remove_strobed_out_invalid_data``. * Drive output signals with ``'X'`` per default when ``valid`` is low in :ref:`bfm.axi_stream_master`. * Rename generics ``data_width_bits`` to ``data_width``, ``id_width_bits`` to ``id_width``, and ``strobe_unit_width_bits`` to ``strobe_unit_width_bits`` in :ref:`bfm.axi_stream_master` and :ref:`bfm.axi_stream_slave`. * Remove default value for ``id_width`` generic, which could potentially hide errors, in :ref:`bfm.axi_slave`, :ref:`bfm.axi_read_slave` and :ref:`bfm.axi_write_slave`. Now the user has to set an explicit value for every instance. * Rework :ref:`axi.axi_write_throttle` concept completely, as part of a bug fix. It is simpler and more light weight now. The ``data_fifo_level`` port as well as all generics have been removed. * Rename generic ``pipeline`` to ``pipeline_axi_lite`` in :ref:`axi_lite.axi_to_axi_lite_vec`. 1.0.0 (20 october 2021) ----------------------- `Changes since previous release `__ Use ``get_hdl_modules()`` call in all ``module_*.py``. 0.0.1 (19 october 2021) ----------------------- First release of the standalone ``hdl-modules`` project. ``modules`` folder copied directly from `tsfpga `__ release ``9.0.0``. See `tsfpga release notes `__ for changelog of earlier releases.