Unreleased (YYYY-MM-DD)

Changes since previous release

Added

• Add handshake_pipeline.vhd generic pipeline_data_signals with default value true, and implement mode that pipelines control signals but not data.

• Add fifo.vhd and asynchronous_fifo.vhd generic enable_output_register, which adds a pipeline stage for RAM output data.

• Add axi_read_master.vhd and axi_write_master.vhd BFMs that create and verify AXI transactions.

• Add axi_read_pipeline.vhd and axi_write_pipeline.vhd blocks that pipeline an AXI bus.

Bug fixes

• Fix full throughput in keep_remover.vhd when not all input lanes are strobed.

• Fix bug in axi_write_throttle.vhd where rogue AW transactions could occur.

Breaking changes

• Change handshake_pipeline.vhd and axi_lite_pipeline.vhd generics allow_poor_input_ready_timing with default value false to pipeline_control_signals with default value True.

• Rename axi_stream_slave.vhd and handshake_slave.vhd generic remove_strobed_out_dont_care to remove_strobed_out_invalid_data.

• Drive output signals with 'X' per default when valid is low in axi_stream_master.vhd.

• Rename generics data_width_bits to data_width, id_width_bits to id_width, and strobe_unit_width_bits to strobe_unit_width_bits in axi_stream_master.vhd and axi_stream_slave.vhd.

• Remove default value for id_width generic, which could potentially hide errors, in axi_slave.vhd, axi_read_slave.vhd and axi_write_slave.vhd. Now the user has to set an explicit value for every instance.

• Rework axi_write_throttle.vhd concept completely, as part of a bug fix. It is simpler and more light weight now. The data_fifo_level port as well as all generics have been removed.

• Rename generic pipeline to pipeline_axi_lite in axi_to_axi_lite_vec.vhd.

1.0.0 (20 october 2021)

Changes since previous release

Use get_hdl_modules() call in all module_*.py.

0.0.1 (19 october 2021)

First release of the standalone hdl_modules project. modules folder copied directly from tsfpga release 9.0.0. See tsfpga release notes for changelog of earlier releases.