Unreleased (YYYY-MM-DD)

Changes since previous release

Breaking changes

Internal changes

  • Optimize library and package imports in a way that decreases simulation time by 20-40% for small testbenches using GHDL.

4.0.0 (25 january 2024)

Changes since previous release

Added

Fixes

  • Fix bug in axi_lite_reg_file.vhd where a non-zero default value for a register of type wpulse or r_wpulse would only be asserted on regs_down the very first clock cycle.

  • Fix bug where axi_read_throttle.vhd could lower ARVALID without an AR transaction having occurred.

Breaking changes

3.0.2 (27 september 2023)

Changes since previous release

Added

3.0.1 (27 september 2023)

Changes since previous release

Added

3.0.0 (2 march 2023)

Changes since previous release

Added

Bug fixes

Breaking changes

  • Rename axi_stream_slave.vhd port num_bursts_checked to num_packets_checked.

  • Rename width_conversion.vhd generic support_unaligned_burst_length to support_unaligned_packet_length.

  • Remove the remove_strobed_out_invalid_data generic from axi_stream_slave.vhd and axi_write_slave.vhd. This behavior is now always enabled.

  • Change to use unresolved VHDL types consistently.

    • std_ulogic instead of std_logic.

    • std_ulogic_vector instead of std_logic_vector.

    • u_signed instead of signed.

    • u_unsigned instead of unsigned.

  • Move to_period and to_frequency_hz functions from types_pkg.vhd to time_pkg.vhd.

  • Remove erroneous assignment of asynchronous_fifo port read_level when packet mode is enabled.

  • Remove the rarely used axi_w_fifo port read_level which does not have valid value in all configurations.

  • Remove the rarely used axi_write_cdc port output_data_fifo_level which does not have valid value in all configurations.

2.0.0 (24 august 2022)

Changes since previous release

Added

Bug fixes

Breaking changes

1.0.0 (20 october 2021)

Changes since previous release

Use get_hdl_modules() call in all module_*.py.

0.0.1 (19 october 2021)

First release of the standalone hdl-modules project. modules folder copied directly from tsfpga release 9.0.0. See tsfpga release notes for changelog of earlier releases.