Module math

This document contains technical documentation for the math module. To browse the source code, please visit the repository on GitHub.

This module contains a contains entities and packages for common math operations in VHDL.


View source code on GitHub.

Package with some common mathematical functions.


View source code on GitHub.

component unsigned_divider is
  generic (
    dividend_width : positive;
    divisor_width : positive
  port (
    clk : in std_ulogic;
    --# {{}}
    input_ready : out std_ulogic;
    input_valid : in std_ulogic;
    dividend : in u_unsigned;
    divisor : in u_unsigned;
    --# {{}}
    result_ready : in std_ulogic;
    result_valid : out std_ulogic;
    quotient : out u_unsigned;
    remainder : out u_unsigned
end component;


dividend / divisor = quotient + remainder / divisor

This is a bit serial divider. Algorithm is the same as long division from elementary school, but with number base two. Latency scales linearly with dividend_width.