Module axi_stream

This document contains technical documentation for the axi_stream module. To browse the source code, please visit the repository on GitHub.

This module contains a set of AXI-Stream components written in VHDL. They are based around record types in axi_stream_pkg.vhd that make it convenient to work with the AXI-Stream signals.

See also the Module bfm for tools to efficiently simulate your AXI-Stream design.


View source code on GitHub.

component axi_stream_fifo is
  generic (
    data_width : positive range 1 to axi_stream_data_sz;
    user_width : natural range 0 to axi_stream_user_sz;
    asynchronous : boolean;
    depth : positive;
    ram_type : ram_style_t
  port (
    clk : in std_ulogic;
    clk_output : in std_ulogic;
    --# {{}}
    input_m2s : in axi_stream_m2s_t;
    input_s2m : out axi_stream_s2m_t;
    --# {{}}
    output_m2s : out axi_stream_m2s_t;
    output_s2m : in axi_stream_s2m_t
end component;

FIFO for AXI Stream. Can be used as clock crossing by setting the asynchronous generic. By setting the width generics, the bus is packed optimally so that no unnecessary resources are consumed.


If asynchronous operation is enabled, the constraints of asynchronous_fifo.vhd must be used.


View source code on GitHub.

Data types for working with AXI4-Stream interfaces. Based on the document “ARM IHI 0051A (ID030610) AMBA 4 AXI4-Stream Protocol Specification” Available here: