Release notes

Release history and changelog for the hdl-modules project. We follow the semantic versioning scheme MAJOR.MINOR.PATCH:

• MAJOR is bumped when incompatible API changes are made.

• MINOR is bumped when functionality is added in a backward-compatible manner.

• PATCH is bumped when backward-compatible bug fixes are made.

Unreleased (YYYY-MM-DD)

Changes since previous release

Nothing here yet.

6.0.0 (18 january 2025)

Changes since previous release

Added

• Add Module dma_axi_write_simple. This module is in a beta state so expect changes in the future.

• Add assign_last.vhd.

• Add resync_rarely_valid.vhd and resync_rarely_valid_lutram.vhd.

• Add resync_sticky_level.vhd.

• Add resync_twophase_lutram.vhd.

Fixed

• Fix bug where asynchronous_fifo.vhd constraint would fail on UltraScale+ devices when FIFO mapped to LUTRAM primitives.

Breaking changes

• Rename resync_slv_level_coherent to resync_twophase.vhd.

• Rename resync_slv_handshake to resync_twophase_handshake.vhd.

• Rename common_pkg.vhd function ite to if_then_else.

• Rename old reg_file module to register_file and rework it. Note that this change is compatible with hdl-registers version 7.0.0 and later. If you use hdl-registers, the changes should be transparent. The changes are:

  • Rename “reg” to “register”, “idx” to “index”, “reg_type” to “mode” for all files, types, constants.

  • Add utilized_width field to register definition type.

  • Optimize resource utilization of axi_lite_register_file.vhd.

  • Remove unused functions.

5.0.1 (9 july 2024)

Changes since previous release

Added

• Add resync_slv_handshake.

• Add enable_iob generic to debounce.vhd.

Bug fixes

• Respect the include_unisim flag in module_hard_fifo.get_simulation_files method.

• Ensure deterministic latency of resync_pulse.vhd, resync_slv_level_coherent, and debounce.vhd.

Other changes

• Waive irrelevant Vivado CDC warnings to make reports more clean.

5.0.0 (8 may 2024)

Changes since previous release

Added

• Add Module sine_generator.

• Add Module lfsr.

• Add saturate_signed.vhd.

Internal changes

• Optimize library and package imports in a way that decreases simulation time by 20-40% for small testbenches using GHDL.

Breaking changes

• Remove protocol checking from handshake_master.vhd and handshake_slave.vhd. If protocol checking is still wanted in places where these are instantiated, an axi_stream_protocol_checker.vhd instance alongside is recommended.

• Split bfm.bfm_pkg into

  • stall_bfm_pkg.vhd

  • axi_slave_bfm_pkg.vhd

  • integer_array_bfm_pkg.vhd

  • queue_bfm_pkg.vhd

  • memory_bfm_pkg.vhd.

• Change stall_config generic of

  • handshake_master.vhd

  • handshake_slave.vhd

  • axi_stream_master.vhd

  • axi_stream_slave.vhd

  • axi_read_master.vhd

  • axi_write_master.vhd

  to use type stall_configuration_t from stall_bfm_pkg.vhd.

4.0.0 (25 january 2024)

Changes since previous release

Added

• Implement our own lightweight axi_stream_protocol_checker.vhd that greatly reduces CPU cycles consumed during simulation.

• Add axi_read_range_checker.vhd and axi_write_range_checker.vhd.

• Add user port to width_conversion.vhd.

Fixes

• Fix bug in axi_lite_register_file.vhd where a non-zero default value for a register of mode wpulse or r_wpulse would only be asserted on regs_down the very first clock cycle.

• Fix bug where axi_read_throttle.vhd could lower ARVALID without an AR transaction having occurred.

Breaking changes

• Remove unused addr_width generic from axi_read_master.vhd and axi_write_master.vhd.

• Rename axi_lite_mux.vhd generic slave_addrs to base_addresses and change type to addr_vec_t, i.e. a list of base addresses. Same for axi_lite_to_vec.vhd generic axi_lite_slaves. The address mask is now calculated internally.

• Rename optional axi_write_master.vhd generic set_axi3_w_id to enable_axi3.

• Remove optional rule_4_performance_check_max_waits generic from handshake_master.vhd and handshake_slave.vhd which is not needed by new axi_stream_protocol_checker.vhd.

• Break axi module into axi_lite and axi_stream.

  • Move from axi to axi_lite:

    • axi_lite_cdc.vhd.

    • axi_lite_mux.vhd.

    • axi_lite_pipeline.vhd.

    • axi_lite_pkg.vhd.

    • axi_lite_simple_read_crossbar.vhd.

    • axi_lite_simple_write_crossbar.vhd.

    • axi_lite_to_vec.vhd.

    • axi_to_axi_lite_vec.vhd.

    • axi_to_axi_lite.vhd.

  • Move from axi to axi_stream:

    • axi_stream_fifo.vhd.

    • axi_stream_pkg.vhd.

3.0.2 (27 september 2023)

Changes since previous release

Added

• Add num_bits_needed_signed to math_pkg.vhd.

3.0.1 (27 september 2023)

Changes since previous release

Added

• Add stable_rising_edge and stable_falling_edge ports to debounce.vhd.

• Add handshake_merger.vhd.

3.0.0 (2 march 2023)

Changes since previous release

Added

• Add handshake_mux.vhd.

• Add clean_packet_dropper.vhd.

• Add time_pkg.vhd.

Bug fixes

• Fix bug where fifo.vhd in packet mode could propagate erroneous data when a packet of length one was written to an almost empty FIFO.

• Fix bug where fifo.vhd and asynchronous_fifo.vhd in packet mode could have bubble cycles in packet readout when output register was enabled.

• Fix bug where axi_stream_master.vhd, axi_write_master.vhd and axi_read_master.vhd would not drive bus with 'X' when valid was low.

Breaking changes

• Rename axi_stream_slave.vhd port num_bursts_checked to num_packets_checked.

• Rename width_conversion.vhd generic support_unaligned_burst_length to support_unaligned_packet_length.

• Remove the remove_strobed_out_invalid_data generic from axi_stream_slave.vhd and axi_write_slave.vhd. This behavior is now always enabled.

• Change to use unresolved VHDL types consistently.

  • std_ulogic instead of std_logic.

  • std_ulogic_vector instead of std_logic_vector.

  • u_signed instead of signed.

  • u_unsigned instead of unsigned.

• Move to_period and to_frequency_hz functions from types_pkg.vhd to time_pkg.vhd.

• Remove erroneous assignment of asynchronous_fifo port read_level when packet mode is enabled.

• Remove the rarely used axi_w_fifo port read_level which does not have valid value in all configurations.

• Remove the rarely used axi_write_cdc port output_data_fifo_level which does not have valid value in all configurations.

2.0.0 (24 august 2022)

Changes since previous release

Added

• Add handshake_pipeline.vhd generic pipeline_data_signals with default value true, and implement mode that pipelines control signals but not data.

• Add fifo.vhd and asynchronous_fifo.vhd generic enable_output_register with default value false, which adds a pipeline stage for RAM output data.

• Add axi_read_master.vhd and axi_write_master.vhd BFMs that create and verify AXI transactions.

• Add axi_read_pipeline.vhd and axi_write_pipeline.vhd blocks that pipeline an AXI bus.

Bug fixes

• Fix full throughput in keep_remover.vhd when not all input lanes are strobed.

• Fix bug in axi_write_throttle.vhd where rogue AW transactions could occur.

• Fix handling of handshake signals in handshake_splitter.vhd to be AXI-Stream compliant.

Breaking changes

• Rework handshake_splitter.vhd to use std_logic_vector for output_ready and output_valid. Introduce mandatory generic num_interfaces.

• Change handshake_pipeline.vhd and axi_lite_pipeline.vhd generics allow_poor_input_ready_timing with default value false to pipeline_control_signals with default value True.

• Rename axi_stream_slave.vhd and handshake_slave.vhd generic remove_strobed_out_dont_care to remove_strobed_out_invalid_data.

• Drive output signals with 'X' per default when valid is low in axi_stream_master.vhd.

• Rename generics data_width_bits to data_width, id_width_bits to id_width, and strobe_unit_width_bits to strobe_unit_width_bits in axi_stream_master.vhd and axi_stream_slave.vhd.

• Remove default value for id_width generic, which could potentially hide errors, in axi_slave.vhd, axi_read_slave.vhd and axi_write_slave.vhd. Now the user has to set an explicit value for every instance.

• Rework axi_write_throttle.vhd concept completely, as part of a bug fix. It is simpler and more light weight now. The data_fifo_level port as well as all generics have been removed.

• Rename generic pipeline to pipeline_axi_lite in axi_to_axi_lite_vec.vhd.

1.0.0 (20 october 2021)

Changes since previous release

Use get_hdl_modules() call in all module_*.py.

0.0.1 (19 october 2021)

First release of the standalone hdl-modules project. modules folder copied directly from tsfpga release 9.0.0. See tsfpga release notes for changelog of earlier releases.