Release notes

Release history and changelog for the hdl_modules project.

Unreleased (YYYY-MM-DD)

Changes since previous release

Nothing here yet.

3.0.0 (2 march 2023)

Changes since previous release

Added

• Add handshake_mux.vhd.

• Add clean_packet_dropper.vhd.

• Add time_pkg.vhd.

Bug fixes

• Fix bug where fifo.vhd in packet mode could propagate erroneous data when a packet of length one was written to an almost empty FIFO.

• Fix bug where fifo.vhd and asynchronous_fifo.vhd in packet mode could have bubble cycles in packet readout when output register was enabled.

• Fix bug where axi_stream_master.vhd, axi_write_master.vhd and axi_read_master.vhd would not drive bus with 'X' when valid was low.

Breaking changes

• Rename axi_stream_slave.vhd port num_bursts_checked to num_packets_checked.

• Rename width_conversion.vhd generic support_unaligned_burst_length to support_unaligned_packet_length.

• Remove the remove_strobed_out_invalid_data generic from axi_stream_slave.vhd and axi_write_slave.vhd. This behavior is now always enabled.

• Change to use unresolved VHDL types consistently.

  • std_ulogic instead of std_logic.

  • std_ulogic_vector instead of std_logic_vector.

  • u_signed instead of signed.

  • u_unsigned instead of unsigned.

• Move to_period and to_frequency_hz functions from types_pkg.vhd to time_pkg.vhd.

• Remove erroneous assignment of asynchronous_fifo port read_level when packet mode is enabled.

• Remove the rarely used axi_w_fifo port read_level which does not have valid value in all configurations.

• Remove the rarely used axi_write_cdc port output_data_fifo_level which does not have valid value in all configurations.

2.0.0 (24 august 2022)

Changes since previous release

Added

• Add handshake_pipeline.vhd generic pipeline_data_signals with default value true, and implement mode that pipelines control signals but not data.

• Add fifo.vhd and asynchronous_fifo.vhd generic enable_output_register with default value false, which adds a pipeline stage for RAM output data.

• Add axi_read_master.vhd and axi_write_master.vhd BFMs that create and verify AXI transactions.

• Add axi_read_pipeline.vhd and axi_write_pipeline.vhd blocks that pipeline an AXI bus.

Bug fixes

• Fix full throughput in keep_remover.vhd when not all input lanes are strobed.

• Fix bug in axi_write_throttle.vhd where rogue AW transactions could occur.

• Fix handling of handshake signals in handshake_splitter.vhd to be AXI-Stream compliant.

Breaking changes

• Rework handshake_splitter.vhd to use std_logic_vector for output_ready and output_valid. Introduce mandatory generic num_interfaces.

• Change handshake_pipeline.vhd and axi_lite_pipeline.vhd generics allow_poor_input_ready_timing with default value false to pipeline_control_signals with default value True.

• Rename axi_stream_slave.vhd and handshake_slave.vhd generic remove_strobed_out_dont_care to remove_strobed_out_invalid_data.

• Drive output signals with 'X' per default when valid is low in axi_stream_master.vhd.

• Rename generics data_width_bits to data_width, id_width_bits to id_width, and strobe_unit_width_bits to strobe_unit_width_bits in axi_stream_master.vhd and axi_stream_slave.vhd.

• Remove default value for id_width generic, which could potentially hide errors, in axi_slave.vhd, axi_read_slave.vhd and axi_write_slave.vhd. Now the user has to set an explicit value for every instance.

• Rework axi_write_throttle.vhd concept completely, as part of a bug fix. It is simpler and more light weight now. The data_fifo_level port as well as all generics have been removed.

• Rename generic pipeline to pipeline_axi_lite in axi_to_axi_lite_vec.vhd.

1.0.0 (20 october 2021)

Changes since previous release

Use get_hdl_modules() call in all module_*.py.

0.0.1 (19 october 2021)

First release of the standalone hdl_modules project. modules folder copied directly from tsfpga release 9.0.0. See tsfpga release notes for changelog of earlier releases.