Release notes

Release history and changelog for the hdl_modules project.

Unreleased (YYYY-MM-DD)

Changes since previous release

Added

Bug fixes

Breaking changes

  • Rename axi_stream_slave.vhd port num_bursts_checked to num_packets_checked.

  • Rename width_conversion.vhd generic support_unaligned_burst_length to support_unaligned_packet_length.

  • Remove the remove_strobed_out_invalid_data generic from axi_stream_slave.vhd and axi_write_slave.vhd. This behavior is now always enabled.

  • Change to use unresolved VHDL types consistently.

    • std_ulogic instead of std_logic.

    • std_ulogic_vector instead of std_logic_vector.

    • u_signed instead of signed.

    • u_unsigned instead of unsigned.

2.0.0 (24 august 2022)

Changes since previous release

Added

Bug fixes

Breaking changes

1.0.0 (20 october 2021)

Changes since previous release

Use get_hdl_modules() call in all module_*.py.

0.0.1 (19 october 2021)

First release of the standalone hdl_modules project. modules folder copied directly from tsfpga release 9.0.0. See tsfpga release notes for changelog of earlier releases.