About hdl-modules

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The hdl-modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks. It is released as open-source project under the very permissive BSD 3-Clause License.

This website contains human-readable documentation of the modules. To check out the source code, go to the GitHub page.

The code is designed to be reusable and portable, while having a clean and intuitive interface. Resource utilization is always critical in FPGA projects, so these modules are written to be as efficient as possible. Using generics to enable/disable different features and modes means that resources can be saved when not all features are used. Some entities are very deliberately area optimized, such as the FIFOs, since they are used very frequently in FPGA projects.

More important than anything, however, is the quality. Everything in this project is peer reviewed, has good unit test coverage, and is proven in use in real FPGA designs. All the code is written with readability and maintainability in mind.

The following things can be found, at a glance, in the different modules:

  • axi: AXI3/AXI4 Crossbars, FIFOs, CDCs, etc.

  • axi_lite: AXI-Lite Crossbars, FIFOs, CDCs, etc.

  • bfm: Many BFMs for simulating AXI/AXI-Lite/AXI-Stream.

  • common: Miscellaneous, but useful, things that do not fit anywhere else.

  • fifo: Synchronous and asynchronous FIFOs with AXI-stream-like handshake interface.

  • hard_fifo: Wrappers, with cleaner AXI-stream-like handshake interfaces, around hard FIFO primitives.

  • math: Some common math function implementations.

  • reg_file: A generic register file and a simulation support package for register operations.

  • resync: Resynchronization implementations for different signals and buses, along with proper constraints.