About hdl_modules

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The hdl_modules project is a collection of reusable, high-quality, peer-reviewed VHDL building blocks. It is released as open source under the very permissive BSD 3-Clause License.

This website contains human-readable documentation of the modules. To check out the source code, go to the gitlab page.

The code is designed to be reusable and portable, while having a clean and intuitive interface. Resource utilization is always critical in FPGA projects, so these modules are written to be as efficient as possible. Using generics to enable/disable different features and modes means that resources can be saved when not all features are used. Some entities are very deliberately area optimized, such as the FIFOs, since they are used very frequently in FPGA projects.

More important than anything, however, is the quality. Everything in this project is peer reviewed, has good unit test coverage, and is proven in use in real FPGA designs. All the code is written with readability and maintainability in mind.

The following things can be found, at a glance, in the different modules:

  • Crossbars, FIFOs, CDCs, etc., for AXI/AXI-Lite/AXI-Stream in the axi module.

  • Many BFMs for simulating AXI/AXI-Lite/AXI-Stream in the bfm module.

  • Some miscellaneous, but useful, things that do not fit anywhere else in the common module.

  • Synchronous and asynchronous FIFOs with AXI-stream-like handshake interface in the fifo module.

  • Wrappers, with cleaner AXI-stream-like handshake interfaces, around hard FIFO primitives in the hard_fifo module.

  • Some common math function implementations in the math module.

  • A generic register file, as well as a simulation package with register BFM operations, in the reg_file module.

  • Resynchronization implementations for different signals and buses, along with proper constraints, in the resync module.